The growing need for continuous processing capabilities has led to thedevelopment of multicore systems with a complex cache hierarchy. Such multicoresystems are generally designed for improving the performance in average case,while hard real-time systems must consider worst-case scenarios. An openchallenge is therefore to efficiently schedule hard real-time tasks on amulticore architecture. In this work, we propose a mathematical formulation forcomputing a static scheduling that minimize L1 data cache misses between hardreal-time tasks on a multicore architecture using communication affinities.
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